High-density FLASH memory devices are used as non-volatile embedded memory or mass-storage devices. For either application, minimizing cell size while maintaining process simplicity is a top priority since every memory chip contains a large number (several million, for example) of cells in arrays which occupy most of the die. A smaller cell translates into a smaller die size and consequently lower manufacturing costs for each die. This is crucial if FLASH memory is to replace magnetic disk drive in mass storage applications.
The two popular types of architecture for high-density FLASH memory are the NAND, which utilizes Fowler-Nordheim (FN) tunneling for both write and erase, and the NOR, which uses channel hot-electron programming and FN tunneling erasure. In recent years, the NAND-type FLASH memory architecture has emerged as the most promising candidate to target the mass storage application. NAND architecture has the distinct advantage of a smaller cell size compared to the other popular NOR-type FLASH memory architecture. The reading or sensing of the content of the data stored in either the NAND-type FLASH cell or NOR-type FLASH cell has been described in other invention disclosures and should be obvious to ones skilled in the art.
One of the main drawbacks of such schemes, which is also a common cause of read error in NAND-type FLASH devices, is that the amount of current sensed by the bitline is not only a function of the content of the selected cell, but it also depends on the content of the other unselected cells that is connected in series together. For example, FIG. 1 illustrates the situation where the selected cell is the last cell is a serial connection of 8 NAND cells together. Assuming the floating gate of the selected cell is depleted of electrons, a channel resistance of about 10 KOhm is associated with the selected cell. If the floating gate of all the unselected cells are programmed, or filled with electrons, the channel resistance for the remaining 7 cells will be about 100 KOhm. This tends to reduce significantly the amount of current that can be sensed by the bitline and leads to a read error since the selected cell can be easily interpreted as "programmed" or filled with electrons due to the high series resistance associated with the other 7 unselected cells. In addition, using the static current to traverse through the high channel resistance will lead to long delay time and high power consumption. This problem has limited the usefulness of NAND architecture to serial access applications. This present invention addresses this problem by proposing a method of displacement current sensing as a way to sense the content of a FLASH memory cell. In addition, the present invention also proposes a new FLASH memory cell structure that is most suitable to be used with the new displacement current sensing scheme.